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Silicon Labs /Series0 /EFM32G /EFM32G890F64 /CMU /LFCLKSEL

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Interpret as LFCLKSEL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)LFA0 (DISABLED)LFB

LFB=DISABLED, LFA=DISABLED

Description

Low Frequency Clock Select Register

Fields

LFA

Clock Select for LFA

0 (DISABLED): LFACLK is disabled

1 (LFRCO): LFRCO selected as LFACLK

2 (LFXO): LFXO selected as LFACLK

3 (HFCORECLKLEDIV2): HFCORECLKLE divided by two or four is selected as LFACLK. The division factor is determined by CMU_CTRL_HFLE and CMU_HFCORECLKDIV_HFCORECLKLEDIV.
LFB

Clock Select for LFB

0 (DISABLED): LFBCLK is disabled

1 (LFRCO): LFRCO selected as LFBCLK

2 (LFXO): LFXO selected as LFBCLK

3 (HFCORECLKLEDIV2): HFCORECLKLE divided by two or four is selected as LFACLK. The division factor is determined by CMU_CTRL_HFLE and CMU_HFCORECLKDIV_HFCORECLKLEDIV.

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
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  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data